Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Design of GHz VLSI clock distribution circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zeng, X. ; Dept. of Electr. Eng., Fudan Univ., Shanghai, China ; Zhou, D.

In this paper, we derive a formula for running the clock signal in a pipeline fashion to meet the GHz frequency challenge. Moreover we present an optimal algorithm for simultaneous balanced planar tree routing and optimal buffer insertion to reach the GHz limit. To ensure the signal integrity, we have developed a very efficient transmission line based simulator, which plays a key role in verifying the clock circuit performance. The proposed method is successfully used to design a real industrial GHz CPU

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference: