By Topic

Evolutionary graph generation system with transmigration capability for arithmetic circuit design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
N. Homma ; Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; T. Aoki ; T. Higuchi

This paper presents a novel graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. This paper also demonstrates that the evolution process of EGG can be accelerated by a simple operation, called “transmigration”, which is to import previously generated good solutions for creating the other solutions

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference: