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Abstractions for model checking of event timings

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4 Author(s)
J. K. Deka ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; S. Chaki ; P. Dasgupta ; P. P. Chakrabarti

Verification of timed temporal properties of a circuit is a computationally complex problem both in terms of space and time. In this paper we study different abstractions of timed systems and the temporal logics which are preserved under these abstractions. In particular we show that while known timed logics such as RTCTL and TCTL are preserved by bisimulation equivalence, the timings of events (signal changes) are preserved in a more compact abstraction. Experimental results show that this abstraction requires significantly less space and is competitive in terms of time required for verification

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Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

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