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Performance estimators for hardware/software co-design

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3 Author(s)
L. Theriault ; Dept. des Sci. Appl., Univ. du Quebec, Chicoutimi, Que., Canada ; D. Auder ; Y. Savaria

This paper proposes hardware/software performance estimators (or metrics) allowing one to analyze the structure of applications written in ANSI C language. These metrics can determine, according to a target architecture, which basic blocks (loops or nested loops) of a gives application are worth embedding into hardware in order to increase the execution speed of the whole application. A FPGA-based reconfigurable system is targeted to implement these blocks

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference: