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An automated process for compiling dataflow graphs into reconfigurable hardware

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8 Author(s)
R. Rinker ; Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA ; M. Carter ; A. Patel ; M. Chawathe
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We describe a system, developed as part of the Cameron project, which compiles programs written in a single-assignment subset of C called SA-C into dataflow graphs and then into VHDL. The primary application domain is image processing. The system consists of an optimizing compiler which produces dataflow graphs and a dataflow graph to VHDL translator. The method used for the translation is described here, along with some results on an application. The objective is not to produce yet another design entry tool, but rather to shift the programming paradigm from HDLs to an algorithmic level, thereby extending the realm of hardware design to the application programmer.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:9 ,  Issue: 1 )