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A simplified, low power 25 MHz CMOS equalizer for disk drive read channels

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2 Author(s)
Pai, P. ; Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA ; Abidi, A.A.

After an extensive study of waveforms measured on several popular disk head-medium combinations, we have found that the combination of the head and medium itself often distorts the read pulse in phase, and a simple equalizer correcting for this phase distortion yields dramatic improvements in bit error rate. This equalizer surprisingly requires only four poles and one zero in the right-half s-plane to perform as well as a conventional flat group delay filter, and its constellation seems to apply to all the packing densities and drive types we have evaluated. We describe here a 2-/spl mu/m CMOS monolithic implementation of this new equalizing filter, with a maximum pole frequency of 25 MHz and an active core power dissipation of only 40 mW from a 5 V supply, including all tuning and subsidiary circuits.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993