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Low-power RF and IF components are essential building blocks for future portable wireless communicators. The conventional view holds that only GaAs or silicon bipolar technologies offer the required gain and low noise at an acceptably low power dissipation in an RF amplifier operating in the 900 MHz frequency band. A wireless transceiver will therefore consist of a mixture of technologies for RF, IF, and baseband signal processing. However, if the entire transceiver is integrated in a single technology, just the elimination of off-chip buffers between the RF and IF sections, say, can lead to considerable power savings. CMOS is the only viable technology for a digital transceiver. To this end, we describe here a 2-/spl mu/m CMOS tuned amplifier affording 14 dB gain centered at 750 MHz, 6 dB noise figure, and 7 mW power dissipation from a 3 V supply. The design of this prototype will be straightforwardly re-centered at 900 MHz in a future version.