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High-speed memories have been used in computers for buffer memory. Such a memory is interconnected with a high-speed arithmetic unit, and the operation cycle-time of memory dominates the performance of computer. Moreover, in order to expand data throughput, it is very advantageous for a high-speed cycle memory to provide a dual-port RAM function, that enables read and write simultaneously. In this paper, a pseudo-dual-port RAM with a 1.5 ns operation cycle is reported. The chip contains 18 kbit RAM (256word x 9bit x 8block) and 9k-gate peripheral logic gates operating during 1.5 ns cycle-time. It is fabricated by a double polysilicon self-aligned bipolar process, using SOI wafer and trench isolation.
Date of Conference: 19-21 May 1993