By Topic

Digital timing recovery circuit with feedback delay compensators for magnetic recording systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Takashi, T. ; Microelectron. Products Dev. Lab., Hitachi Ltd., Yokohama, Japan ; Miyazawa, S. ; Iwabuchi, K. ; Shimura, Y.
more authors

Timing recovery circuits in magnetic recording systems have to have high bit rate and fast acquisition cycles, so they are usually equipped with an analog phase-locked loop (PLL). We propose a new method of digital timing recovery circuit that is different from the conventional digital PLL and that can be operated under a faster acquisition and wider capture range. This report describes the new digital timing recovery circuit architecture for magnetic recording that uses feedback delay compensators for fast acquisition and wide capture range on CMOS LSI circuit.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993