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16 Mbit synchronous DRAM with 125 Mbyte/sec data rate

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13 Author(s)
Yunho Choi ; Product Dev. Center, Samsung Electron. Co., Suwon, South Korea ; Myungho Kim ; Taejin Kim ; Seung-Hoon Lee
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The rapid increase in processor performance and memory density has created the need for high bandwidth DRAM for a variety of applications. A 3.3V 2M x8 synchronous DRAM is designed with a typical data rate of 125 Mbyte/sec using internal column address sequencing, pipelined 2 bit prefetch and variable output latching scheme. It supports operating frequencies up to 125 MHz.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993