Referenced Items are not available for this document.
Subthreshold-current reduction, especially at room-temperature operation, is one of the key design issues in the gigabit era. Despite its importance, however, a scheme for it has not been proposed. In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed. They can drastically reduce even the active current of a 16 Gbit DRAM by one tenth, from 1.2A to 116mA.
Published in:
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Date of Conference: 19-21 May 1993
- Page(s):
- 45 - 46
- INSPEC Accession Number:
- 4764467
- Conference Location :
- Kyoto, Japan
- Digital Object Identifier :
- 10.1109/VLSIC.1993.920532
- Product Type:
- Conference Publications
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