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Subthreshold-current reduction circuits for multi-gigabit DRAM's

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3 Author(s)
Sakata, T. ; Central Res. Lab., Hitachi Ltd., Kokubunji, Japan ; Horiguchi, M. ; Itoh, K.

Subthreshold-current reduction, especially at room-temperature operation, is one of the key design issues in the gigabit era. Despite its importance, however, a scheme for it has not been proposed. In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed. They can drastically reduce even the active current of a 16 Gbit DRAM by one tenth, from 1.2A to 116mA.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993