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A charge recycle refresh for Gb-scale DRAMs in file applications

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7 Author(s)
T. Kawahara ; Central Res. Lab., Hitachi Ltd., Kokubunji, Japan ; M. Horiguchi ; Y. Kawajiri ; T. Akiba
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A low-power charge recycle refresh featuring alternative operation of two arrays was proposed. After amplification in the first array, the charges in that array are transferred to the other array, where they are recycled for half the amplification there. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is also reduced. This technique can reduce the data retention current in Gb-scale or subGb-scale DRAMs, where the reduction of data-retention current by extending the refresh period is limited by the cell retention time.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993