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This mixed analog-digital fuzzy logic inference processor chip calculates the result of an inference over a 32-rule knowledge base in parallel. Simulations predict a computation time for the array of about 2 /spl mu/sec. The processor interface behaves like a static RAM, but internal computation is performed in the analog domain to an expected precision of 6 bits. The completed chip measures 7 mm by 10 mm in a 0.8 /spl mu/m CMOS technology, and is currently undergoing preliminary testing.