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The synchronous Tag RAM reported in this paper holds addresses and status bits of cached data and can be used to build a secondary cache system of up to 16MBytes with external commodity synchronous SRAMs. In order to handle the large secondary cache, the present Tag RAM contains 1.189Mbit of 4T SRAM cells, the largest capacity ever reported for a Tag RAM. Short cycle time and small clock to D/sub OUT/ (data output) delay of the Tag RAM is crucial for a high-performance cache system. 9ns cycle operation and clock to D/sub OUT/ of 4.7ns in typical condition are achieved by a use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, a highly linear Voltage-Controlled Oscillator (VCO) for a Phase Locked Loop (PLL) and doubly placed self-timed write circuits. Since pure CMOS implementation cannot achieve the required speed, the device is manufactured with 0.7/spl mu/m double-polysilicon and double-metal BiCMOS technology.