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Recently, the demand for using low-end RISC-CPUs in small equipment devices such as handy terminals is increasing. On-chip cache and direct connections to page mode DRAM is one of the best solution to achieve high-performance and low-cost systems. However, integrating the conventional cache will have a penalty of cache miss increase when page mode DRAM is used for burst transfer mode. This paper describes a new on-chip small instruction cache (called Variable Line Length Cache) for low-end RISC CPU. When a cache-miss signal occurs, this cache continuously reloads, pre-fetches and supplies the instructions though it consists of conventional RAMs. With this new cache, the reduction of the total waits is 20 to 30 percent less compared to the conventional cache when it is adapted to the application specified RISC processor, so that the new cache improves the cache hit ratio.