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Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to be relatively long. Consequently, the tradeoffs between clock rate and superscalar complexity should be carefully examined. In this paper, we describe a superscalar RISC processor which attains high operation speed.