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Design for testability of sequential circuits

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1 Author(s)
Kinoshita, K. ; Dept. of Appl. Phys., Osaka Univ., Japan

In this paper we applied the method known as checking experiments to generate test sequences for sequential circuits under the stuck-at fault model. To design a sequential circuit having a distinguishing sequence is a key in this method. As modification techniques of sequential circuits, two testable design techniques have been considered. One is a testable design technique at the state transition level and the other is at the gate level. We have also shown that it is possible to shorten the test sequence by using a fault simulator. Experimental results show that fault coverages for all stuck-at faults have reached 100% for the circuits under designed for testability both at the state transition level and at the gate level. As a result, it has been shown that the distinguishing sequence is very useful for test generation of sequential circuits.

Published in:

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Date of Conference:

19-21 May 1993