By Topic

Testing asynchronous circuits: help is on the way!

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

Summary form only given. The author describes the synergies in test problems with synchronous designs that will help in the testing of asynchronous designs. In particular, he touches upon the ATE architectures and points out where the current architectures are inadequate in supporting the testing of asynchronous circuits. The author then describes the current and planned features in ATEs that will be helpful in testing asynchronous circuits. Other topics covered include: Design for Testability (DFT); test generation; test translation; and test time management, where the development in synchronous circuit domain can be used as platform to build similar capabilities for asynchronous circuits

Published in:

Asynchronus Circuits and Systems, 2001. ASYNC 2001. Seventh International Symposium on

Date of Conference:

2001