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AMULET3i cache architecture

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2 Author(s)
Hormdee, D. ; Dept. of Comput. Sci., Manchester Univ., UK ; Garside, J.D.

This paper presents an evaluation of a range of cache features applied to an asynchronous, dual-ported copy-back cache. The design has been optimised for the AMULET3 asynchronous microprocessor core, but the techniques developed are much more widely applicable. It is shown that using a copy-back cache with a victim cache would gives a noticeable performance improvement on the existing fabrication technology and that the benefits will increase with increasing cache/memory speed disparity. The design presented provides the processor with a unified, dual-ported view of its memory subsystem using multiple interleaved blocks each with separate line-buffers

Published in:

Asynchronus Circuits and Systems, 2001. ASYNC 2001. Seventh International Symposium on

Date of Conference:

2001