An asynchronous superscalar architecture for exploiting instruction-level parallelism

This paper proposes an asynchronous superscalar architecture called DCAP to exploit instruction-level parallelism based on a novel dynamic instruction scheduling technique. The proposed technique not only has an efficient implementation using asynchronous micropipelines, it also minimizes the amount of hardware required for instruction scheduling when compared to standard schemes used in synchronous superscalar processors. In addition, the proposed technique for dynamic instruction scheduling also exploits the dependency patterns in the instruction streams for enhanced performance. DCAP is a fully functional model of an asynchronous superscalar processor and supports register renaming and precise interrupts. A detailed performance analysis of DCAP on realistic benchmarks is presented.