Design planning for single chip implementation of digital wireless mobile transceiver

In this paper, we present a design planning paradigm for the design of a wireless mobile transceiver. We consider the digital part in a single chip implementation of a transceiver based on the CDMA spread spectrum technique. The complexity of such a chip implementation makes the design process complex and very expensive. The desired characteristics of a mobile transceiver are low cost, small size, and low power. Design cost forms a major portion of total system cost. In order to reduce design cost, design completion time should be reduced. We assume hardware-software design flow for design of the transceiver. We analyze the design flow using the hierarchical concurrent flow graph (HCFG) approach. We illustrate, using AND and OR concurrent constructs of the HCFG approach, how the design process completion time can be reduced by employing concurrent design efforts. We also present an approach for completion time improvement which considers the sensitivity of completion time with respect to task completion time and probabilities. HCFG analysis facilitates a pre-execution “what-if” analysis to determine the suitable design flow which provides lowest process completion time