A parallel compact genetic algorithm for multi-FPGA partitioning

In this paper we investigate the design of a compact genetic algorithm to solve multi-FPGA partitioning problems. Nowadays Multi-FPGA systems are used for a great variety of applications such as dynamically reconfigurable hardware applications, digital circuit emulation, and numerical computation. Both a sequential and a parallel version of a compact genetic algorithm (cGA) have been designed and implemented on a cluster of workstations. The peculiarities of the cGA permits to save memory in order to address large multi-FPGA partitioning problems, while the exploitation of parallelism allows to reduce execution times. The good results achieved on several experiments conducted on different multi-FPGA partitioning instances show that this solution is viable to solve multi-FPGA partitioning problems.