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Dynamic fault tolerance in FPGAs via partial reconfiguration

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4 Author(s)
J. Emmert ; Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA ; C. Stroud ; B. Skaggs ; M. Abramovici

In this paper we present an on-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our method is based on the roving self testing areas (STARs) fault detection/location strategy presented in Abramovici et al. (1999). In STARs, the area under test uses partial reconfiguration properties to modify the configuration of the area under test without affecting the configuration of the system function and dynamic reconfiguration properties to allow uninterrupted execution of the system function while reconfiguration takes place. In this paper we take this one step further. Once a fault (or multiple faults) is detected we dynamically reconfigure the working area application around the fault with no additional system function interruption (other than the interruption when a STAR moves to a new location). We also apply the concept of partially usable blocks to increase fault tolerance. Our method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies

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Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on

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