Referenced Items are not available for this document.
A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-serial architecture to perform multiplication modulo 216+1, the implementation occupies a minimal amount of hardware. The bit-serial architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125 MHz on a Xilinx Virtex XCV300-6, delivering a throughput of 500 Mb/sec. With a XCV1000-6 device, the estimated performance is 2 Gb/sec, three orders of magnitude faster than a software implementation on a 450 MHz Intel Pentium II. This design is suitable for applications in on-line encryption for high-speed networks
Published in:
Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on
Date of Conference: 2000
- Page(s):
- 122 - 131
- Meeting Date :
- 17 Apr 2000-19 Apr 2000
- Print ISBN:
- 0-7695-0871-5
- INSPEC Accession Number:
- 6853659
- Conference Location :
- Napa Valley, CA
- Digital Object Identifier :
- 10.1109/FPGA.2000.903399
- Product Type:
- Conference Publications
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