Referenced Items are not available for this document.
Switching noise and ultra deep sub-micron designs is assuming increasing proportions due to decreased rise times, scaled features sizes and interconnect complexity. Moreover, to achieve higher frequencies the use of different logic families is explored, where contribution in terms of noise generation is not completely defined. In the paper we report some results from a detailed simulation sequence performed to define clearly the influence of technological parameters and of the use of different logic families with respect to noise generation. The aim is to use this information in a developing CAD tool for switching noise free placement
Published in:
VLSI Design, 2001. Fourteenth International Conference on
Date of Conference: 2001
- Page(s):
- 524 - 530
- Meeting Date :
- 03 Jan 2001-07 Jan 2001
- ISSN :
- 1063-9667
- Print ISBN:
- 0-7695-0831-6
- INSPEC Accession Number:
- 6894350
- Conference Location :
- Bangalore
- Digital Object Identifier :
- 10.1109/ICVD.2001.902711
- Product Type:
- Conference Publications
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