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Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic

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3 Author(s)
H. Soeleman ; Purdue Univ., West Lafayette, IN, USA ; K. Roy ; B. Paul

Sub-threshold static and ratioed logic have recently been proposed to satisfy the ultra-low power requirement in applications such as hearing aids, pace-makers, wearable wrist-watch computers etc. These logic circuits, however, can be operated only at lower frequencies due to lower supply voltage. To increase the frequency of operation, we propose sub-threshold dynamic logic: Sub-Domino logic. A standard full-adder circuit is implemented in both Sub-Domino and Sub-CMOS logic operating in the subthreshold region. Simulation results show that Sub-Domino logic has lower power consumption, smaller area (60% of Sub-CMOS logic), and is 3 times faster than Sub-CMOS logic. It is also shown that Sub-Domino logic has excellent noise margin

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:

2001