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Design of provably correct storage arrays

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3 Author(s)
Joshi, R.V. ; Div. of Res., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Hwang, W. ; Kuehlmann, A.

In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register transfer level (RTL) specification with a low-level transistor implementation. Equivalence checking is increasingly applied in practical design flows to verify regular logic components. However, because of their specific organization and circuit techniques, high-performance implementations of large storage arrays require particular modifications to the general flow that make them suitable for formal equivalence checking. Two techniques are outlined in this paper. First, a special hierarchical verification scheme is described that allows the application of a partitioned comparison approach of the bit-wise organized transistor-level model with the word-wise organized RTL model. Second, a modified switch-level extraction technique is presented that extends the applicability of equivalence checking from regular dynamic CMOS circuits to self-resetting CMOS (SRCMOS) circuits

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VLSI Design, 2001. Fourteenth International Conference on

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