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Timing verification and delay test generation for hierarchical designs

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3 Author(s)
Krishnamachary, A. ; Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA ; Abraham, J.A. ; Tupuri, R.S.

This paper develops an effective solution for timing verification and delay test generation at the full chip level by exploiting the hierarchy in large designs. Currently, timing verification can only be done at the module level. We consider the timing verification problem when a module is instantiated in a larger design, where the module-level critical paths might no longer hold. In order to check whether a module-level critical path is true at the chip level, we use a fault injection circuit where detecting a stuck-at fault in this circuit will result in a pair of vectors which sensitize the critical path in the module. Unfortunately, existing sequential automatic test pattern generators (ATPG) cannot deal with complete chip designs in generating tests using the above approach. Therefore, we use a hierarchical test generation approach which abstracts the rest of the large chip into just the logic behavior relevant to the embedded module. This resulting reduction in complexity allows us to identify chip-level critical paths in large designs and to find delay tests for sensitizing these true critical paths. Experimental results confirm that the proposed technique is able to validate all the module-level critical paths in processor designs and show that most of the module-level critical paths are false at the chip level, while commercial ATPG at the full-chip level aborts in all the cases

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference: