On fault-simulation through embedded memories on large industrial designs

Modern microprocessor designs contain several embedded memory arrays that form register files, caches, TLBs, re-order buffers, etc. These arrays are an integral portion of the design and may sometimes drive substantial data-path and control logic blocks in a microprocessor. Fault-simulation and ATPG for state-of-the-art commercial microprocessor designs is complex and requires suitable engineering to make them successful. In this paper we discuss a framework for fault-simulation of large microprocessor designs containing hundreds of embedded memory arrays in use today. Embedded memory arrays come in a variety of flavours with different number of input and output ports and different access mechanisms. In this paper we discuss how these arrays can be described for the fault-simulator and present the data-structures and some of the algorithms for simulating faults through these arrays.