By Topic

Optimizing the cost of design rule modifications for subsequent generations of semiconductor technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Balasinski, Artur ; Cypress Semicond., San Jose, CA, USA

Progress in semiconductor manufacturing requires that device dimensions shrink for every subsequent generation of technology. This shrinking can be accomplished by the corresponding scaling of design databases, generated using a predetermined set of design rules. However, establishing a common shrink factor for all design rules used in the layout presents a formidable task. An aggressive scaling by a large shrink factor may result in limited manufacturability of a product whereas a safe approach using a small shrink factor may compromise the competitiveness of a product line. In this work, we propose cost and benefit driven approach to the rule scalability. The controversial rules that would affect new product development are first defined followed by the cost comparison between the redesign and process development. Example rules are defined and used to demonstrate how to optimize the procedure based on spreadsheet calculations

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

Date of Conference:

2000