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SCIMA: a novel architecture for high performance computing

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5 Author(s)
H. Nakamura ; Res. Center for Adv. Sci. & Technol., Tokyo Univ., Japan ; H. Okawara ; T. Boku ; M. Kondo
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Technological trends have brought growing disparity between processor and memory speeds. This memory wall problem is becoming very serious especially in high performance computing. In this paper, we propose a new architecture SCIMA for solving this problem. In SCIMA, addressable memory is integrated into the processor chip besides ordinary cache. Since the on-chip memory is software controllable, it has more ability to make good use of data locality than data cache which is controlled by hardware. The purpose of on-chip memory is to reduce the off-chip memory traffic by exploiting data reusability as much as possible within a chip. We have evaluated SCIMA by using QCD simulation, a practical application in quantum field theory. The performance evaluation reveals that SCIMA successfully reduces off-chip memory traffic and achieves higher performance than cache-only processor

Published in:

Innovative Architecture for Future Generation High-Performance Processors and Systems, 1999. International Workshop

Date of Conference:

Dec 2000