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Test program synthesis for path delay faults in microprocessor cores

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3 Author(s)
Wei-Cheng Lai ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Krstic, A. ; Kwang-Ting Cheng

This paper addresses the problem of testing path delay faults in a microprocessor core using its instruction set. We propose to self-test a processor core by running an automatically synthesized test program which can achieve a high path delay fault coverage. This paper discusses the method and the prototype software framework for synthesizing such a test program. Based on the processor's instruction set architecture, micro-architecture, RTL netlist as well as gate-level netlist on which the path delay faults are modeled, the method generates deterministic tests (in the form of instruction sequences) by cleverly combining structural and instruction-level test generation techniques. The experimental results for two microprocessors indicate that the test instruction sequences can be successfully generated for a high percentage of testable path delay faults

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Test Conference, 2000. Proceedings. International

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