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On validating data hold times for flip-flops in sequential circuits

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6 Author(s)
S. M. Reddy ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; I. Pomeranz ; S. Kajihara ; A. Murakami
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We consider the problem of validating flip-flop data hold time requirements in sequential circuits. The data hold time violations considered are related to the presence of short paths that allow changes in next-state values to occur fast enough so as to cause latching of erroneous next-states. Three fault models are proposed that are related to the presence of short paths in the circuit. Propagation conditions for robust and non-robust tests for short paths are given. A test generation procedure is described for one of the proposed models, and experimental results are provided for benchmark circuits

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Test Conference, 2000. Proceedings. International

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