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Enhanced untestable path analysis using edge graphs

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4 Author(s)
Kajihara, S. ; Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan ; Shimono, T. ; Pomeranz, I. ; Reddy, S.M.

Logic circuits may have large numbers of untestable paths. Therefore, it is important for path delay fault testing to identify untestable paths prior to test generation. An earlier method, called partial path sensitization, was able to identify large numbers of untestable path delay faults by analyzing pairs of subpaths. We propose to apply this method to the edge graph of the circuit. In the edge graph, an edge corresponds to two consecutive subpaths. Thus, identification of untestable paths is done based on longer subpaths when the edge graph is used than when the original netlist is used. Experimental results presented in this paper show that the proposed method identifies more untestable paths than when the partial path sensitization method is applied to the original netlist

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Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Date of Conference: