In this paper, a new approach is presented for the transit time calculations in fast silicon planar photodiodes operating at low-voltage bias. It is shown that at a given voltage bias the transit time has a minimal value at certain carrier concentrations in the high-resistive layer. Results presented are useful for correct design optimization of the device
Published in:
Semiconductor Conference, 2000. CAS 2000 Proceedings. International
(Volume:2
)
Date of Conference: 2000