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3-D packaging methodologies for microsystems

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4 Author(s)
G. Kelly ; Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland ; A. Morrissey ; J. Alderman ; H. Camon

Issues associated with the packaging of microsystems in plastic and three-dimensional (3-D) body styles are discussed. The integration of a microsystem incorporating a micromachined silicon membrane pump, into a 3-D plastic encapsulated vertical multichip module package (MCM-V) is described. Finite element techniques are used to analyze the encapsulation stress in the structure of the package. Cracks develop in the chip carrier due to thermomechanical stress. Based on the results of a finite element design study, the structures of the chip carriers are modified to reduce their risk of cracking. Alternative low stress 3-D packaging methodologies based on chip on board and plastic leadless chip carriers are discussed.

Published in:

IEEE Transactions on Advanced Packaging  (Volume:23 ,  Issue: 4 )