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Memory system energy: Influence of hardware-software optimizations

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4 Author(s)
G. Esakkimuthu ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; N. Vijaykrishnan ; M. Kandemir ; M. J. Irwin

A memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms (block buffering and sub-banking) and three widely used compiler optimization techniques (linear loop transformation, loop tiling, and loop unrolling). Our results show that the pure hardware optimizations (eight block buffers and four sub-banks in a 4K, 2-way cache) provided up to 4% energy saving, with an average saving of 2% across all benchmarks. In contrast, the pure software optimization approach that uses all three compiler optimizations, provided at least 23% energy saving, with an average of 62%. However, a closer observation reveals that hardware optimization becomes more critical for on-chip cache energy reduction when executing optimized codes.

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Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

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