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Noise-aware power optimization for on-chip interconnect

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5 Author(s)
Ki-Wook Kim ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Seong-Ook Jung ; Narayanan, U. ; Liu, C.L.
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Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.

Published in:

Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

Date of Conference:

2000