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Optimization of high-performance superscalar architectures for energy efficiency

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2 Author(s)
Zyuban, V. ; Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA ; Kogge, P.

In recent years reducing power has become a critical design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization at the micro-architectural level. First, major targets for power reduction are identified within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energy-efficient configurations forming a convex hull in the power-performance space. The energy-efficient families are then compared to find configurations that dissipate the lowest power given a performance target, or, conversely, deliver the highest performance given a power budget. Application of the developed methodology to a superscalar microarchitecture shows that at the architectural level there is a potential for reducing power up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget.

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Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

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