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Analyzing the test generation problem for an application-oriented test of FPGAs

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5 Author(s)
Renovell, M. ; LIRMM-UM2, Montpellier, France ; Portal, J.M. ; Faure, P. ; Figueras, J.
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The objective of this paper is to generate an application-oriented test procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of `AC-non-redundant fault'. Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description

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Test Workshop, 2000. Proceedings. IEEE European

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