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Static and dynamic on-chip test response evaluation using a two-mode comparator

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3 Author(s)
De Venuto, D. ; Dip. di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy ; Ohletz, M.L. ; Matarrese, G.

A design-for-testability implementation to achieve high fault coverages in the analogue functional blocks of mixed circuit ASICs is presented in this feasibility study. To this end existing op amps or OTAs are converted into clocked comparators with hysteresis and variable reference levels. The resulting two-mode comparators are connected to specific internal nodes. Depending on the mode this node can be either statically and/or dynamically evaluated on-chip without the need to bring an analogue signal off-chip. Results from first simulations and measurements on a test circuit realised in 0.35 μm technology are presented

Published in:

Test Workshop, 2000. Proceedings. IEEE European

Date of Conference:

2000