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Bridging the testing speed gap: design for delay testability

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4 Author(s)
Speek, H. ; MESA Res. Inst., Twente Univ., Enschede, Netherlands ; Kerkhoff, H.G. ; Sachdev, M. ; Shashaani, M.

The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed

Published in:

Test Workshop, 2000. Proceedings. IEEE European

Date of Conference:

2000

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