Thru-silicon vias for 3D WLP
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Thru-Silicon designs and manufacturing process flows are introduced as a means to produce 3D wafer level packaging solutions. Standard silicon IC manufacturing unit-processes must be combined into robust process-flows to allow for the rapid deployment of wafer-level packaging throughout the industry
Published in:
Advanced Packaging Materials: Processes, Properties andInterfaces, 2000. Proceedings. International Symposium on
Date of Conference: 2000