By Topic

Optimizing memory bandwidth with ILP based memory exploration and assignment for low power embedded systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Wen-Tsong Shiue ; Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA

In this paper, we describe a low power memory design procedure that optimizes memory bandwidth in VLSI sytems. We develop the procedures of loop transformation to optimize the memory cost for the required storage bandwidth. Next, we develop memory assignment based on ILP model that is derived from mapping graph (MG) such that we can find (i) the best memory configuration (minimum-area memory configuration if power is bound or minimum-power memory configuration if area is bound) and (ii) the power/area efficient array assignment to given memory library (the number of memory banks, the number of ports, and the total memory size)

Published in:

Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

Date of Conference:

2000