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A simple built-in self test for dual ported SRAMs

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1 Author(s)
K. Truong ; Cadence Design Syst. Inc., San Jose, CA, USA

This paper presents a discussion on a simple memory Built-In Self Test (BIST) design for dual ported SRAM that concurrently applies a modified March test to both ports of an embedded SRAM. It begins by outlining the role of embedded dual ported SRAM in today's ASICs., briefly discusses how commercial memory test tools deal with dual ported SRAMs and the difficulties to realistically cover the complex coupling faults which are suspected to expose memory errors at the system level. Subsequently this paper examines the MARCH test for modification to enable the development of a simple BIST architecture that can be designed for concurrent testing of both ports with minimum extra cost

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Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

Date of Conference: