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Diagnosing the interconnect of bus-connected multi-RAM systems under restricted and general fault models

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3 Author(s)
Jun Zhao ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Meyer, F.J. ; Lombardi, Fabrizio

This paper presents new approaches for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short, open and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Detection and maximal diagnosis are considered under a restricted fault model (short faults only) as well as a general fault model (all types of faults)

Published in:

Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

Date of Conference:

2000