An efficient algorithm for multidimensional convolution

This paper presents a novel recursive algorithm for generating higher-order multidimensional (or m-D for short) convolution by combining the computation of 3/sup m/ identical lower-order (smaller size) convolution computations, and its implementation in parallel VLSI networks. We show that for 2-D convolutions, with careful design, the number of lower-order 2-D convolutions can be reduced from nine to six with a computation saving of 35%. The resulting VLSI architectures have very simple modular structure, highly regular topology, and use simple arithmetic units.