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A channel-select filter with on-chip PLL tuning for CDMA IS-95 has been integrated in a 0.35-/spl mu/m digital CMOS technology. To achieve both low power and robustness, dynamic range scaling is implemented on an elliptic ladder prototype. The dynamic range scaling is based on the special requirement for the wireless receiver. A new method to analyze the trade-off between filter noise and power consumption is presented. The filter and PLL dissipate 2.9 mW and 1.6 mW from a 3-V supply, and the die area is 1.06 mm/sup 2/. The filter achieves 61 dB stopband rejection, 0.05 dB/0.2/spl deg/ I/Q gain/phase mismatch, 100 /spl mu/Vrms input-referred noise, 20 dBm IIP3, and 58 dB SFDR.