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A 2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 /spl mu/m CMOS bulk technology

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6 Author(s)
Joshi, R.V. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Kowalczyk, S.P. ; Chan, Y.H. ; Huott, W.V.
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This paper describes a high speed L1 directory (34 Kb) with read access time below 430 ps and a cycle of 2 GHz in 1.5 V, 0.18 /spl mu/m CMOS bulk technology. The key features of this high performance dynamic design are fast static input/output interface with the provision of converting internal signals from static to dynamic and then back to static at the output, L1/L2 latches at the input, modular building blocks, pseudo-static circuits, robust timing plan and capability for extensive test pattern coverage and access time evaluation using a programmable "Array-Built-In-Self-Test" (ABIST).

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000