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A dual page programming scheme for high-speed multi-Gb-scale NAND flash memories

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2 Author(s)
K. Takeuchi ; Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan ; T. Tanaka

The increasing demand for portable mass storage applications has created a need for a high-density and high-speed programming flash memory. One way to increase the program throughput is to increase the page size, i.e., the number of memory cells programmed simultaneously. But this requires additional page buffers and increases the chip size. To solve this problem, we propose a new programming scheme, where the page size is doubled without increasing the page buffers. The programming is accelerated by 73% in a 4 Gb product and 62% in a 4 Gb product without area penalty. 18.2 MB/sec 1 Gb or 30.7 MB/sec 4 Gb NAND flash memory can be realized with this new architecture.

Published in:

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Date of Conference:

15-17 June 2000